As semiconductor devices become more highly integrated, the size of gate patterns can be reduced which can change an electrical property associated with the gate pattern. For example, where a metal silicide, such as tungsten silicide, is used as a gate pattern, resistance of the gate pattern can increase (sometimes relatively rapidly) as size of the gate pattern is reduced. Thus, in order to adjust for the resistance increase caused by the reduced size gate pattern in a highly integrated semiconductor device, a metal (such as tungsten) having a low resistance can be used to offset the increased resistance caused by the reduced size gate pattern.
FIG. 1 is a cross-sectional diagram of a semiconductor device having a metal gate electrode according to the prior art. Referring to FIG. 1, a gate insulator 3, a gate polysilicon layer 5, a barrier metal layer 7, a metal gate layer 9, and a capping layer 11 are sequentially formed and patterned to form a gate pattern 13. In order to treat etch damage that can occur at the semiconductor substrate 1 and the gate polysilicon layer 5 during the patterning process, a thermal treatment process can be performed in an oxygen environment. At this time, as shown in FIG. 1, oxygen may diffuse through a side surface of the metal gate layer 9 while thermal treating under the oxygen environment, thereby forming an oxide layer “O” at a boundary between the metal barrier layer 7 and the gate polysilicon layer 5. The oxide layer “O” may increase resistance between the metal gate layer 9 and the gate polysilicon layer 5. The increased resistance attributed to the oxide layer may result in one or more of an RC (time constant) delay, a lower operational speed and reliability in a semiconductor device.